Supermicro SYS-5013C-MT Datový list stáhnout pdf (Strana 12)

1-2

SUPERSERVER 5013C-MT User's Manual

1-2 Motherboard Features

At the heart of the SuperServer 5013C-MT lies the P4SCT+, a single pro-

cessor motherboard designed to provide maximum performance. Below are

the main features of the P4SCT+.

Chipset Overview

The P4SCT+ is based on Intel’s E7210 chipset (see Figure 1-1 for a block

diagram). The E7210 chipset is made up of two main components:

The Memory Controller Hub (MCH)

The I/O Controller Hub (6300ESB)

Memory Controller Hub (MCH)

The MCH controls the flow of data between the host (CPU) interface, the memory

interface and the I/O Controller Hub interface. It contains advanced power man-

agement logic and supports dual-channel (interleaved) DDR memory, providing

bandwidth of up to 6.4 GB/s using DDR400 SDRAM. The MCH supports configu-

rations of a 800 MHz FSB with a 400/333 memory interface, a 533 MHz FSB with

a 333/266 memory interface, and a 400 MHz FSB with a 266 MHz memory

interface.

The MCH supports 128 MB, 256 MB, 512 MB, 1 GB, x4, x8, and x16 DDR.

Maximum system memory supports up to 4.0 GB for dual-channel, ECC or Non-

ECC unbuffered DDR. Registered and/or mixed-mode DIMMs are not supported.

For more information, please refer to Chapter 5.

I/O Controller Hub (6300ESB)

The 6300ESB ICH provides the I/O subsystem with access to the rest of the

system. It integrates a dual-channel Ultra ATA/100 bus master IDE controller,

the SMBus 2.0 controller, the LPC/Flash BIOS interface, the PCI-X (66MHz) 1.0

interface, the PCI 2.2 interface and the System Management Controller.

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 111 112

Žádné komentáře

Supermicro SYS-5013C-MT Datový list Strana 12