Supermicro HMT325R7BFR8C-H9 Specifikace

Rev. 1.6 / Dec. 2010 1 2Gb DDR3 SDRAM2Gb DDR3 SDRAMLead-Free&Halogen-Free(RoHS Compliant)H5TQ2G83BFR-xxCH5TQ2G83BFR-xxIH5TQ2G63BFR-xxCH5TQ2G63BFR-

Rev. 1.6 / Dec. 2010 10 Absolute Maximum RatingsAbsolute Maximum DC RatingsDRAM Component Operating Temperature RangeAbsolute Maximum DC RatingsSymbol

Rev. 1.6 / Dec. 2010 11 AC & DC Operating ConditionsRecommended DC Operating ConditionsRecommended DC Operating ConditionsSymbol ParameterRatingUn

Rev. 1.6 / Dec. 2010 12 IDD and IDDQ Specification Parameters and Test ConditionsIDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ meas

Rev. 1.6 / Dec. 2010 13 Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements[Note: DIMM level Output test load conditio

Rev. 1.6 / Dec. 2010 14 Table 1 -Timings used for IDD and IDDQ Measurement-Loop PatternsTable 2 -Basic IDD and IDDQ Measurement ConditionsSymbolDDR3-1

Rev. 1.6 / Dec. 2010 15 IDD2NPrecharge Standby CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, A

Rev. 1.6 / Dec. 2010 16 IDD3PActive Power-Down CurrentCKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Ad

Rev. 1.6 / Dec. 2010 17 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_No

Rev. 1.6 / Dec. 2010 18 Table 3 - IDD0 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-L

Rev. 1.6 / Dec. 2010 19 Table 4 - IDD1 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, ot

Rev. 1.6 / Dec. 2010 2 Revision HistoryRevision No. History Draft Date Remark0.1 Initial Release Dec. 20090.2 Added IDD Specification Feb. 20101.0 Add

Rev. 1.6 / Dec. 2010 20 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signa

Rev. 1.6 / Dec. 2010 21 Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD

Rev. 1.6 / Dec. 2010 22 Table 8 - IDD4W Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands,

Rev. 1.6 / Dec. 2010 23 Table 10 - IDD7 Measurement-Loop Patterna)ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loo

Rev. 1.6 / Dec. 2010 24 IDD SpecificationsIDD values are for full operating range of voltage and temperature unless otherwise noted.IDD SpecificationN

Rev. 1.6 / Dec. 2010 25 Input/Output CapacitanceParameter SymbolDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133Units NotesMin Max Min Max M

Rev. 1.6 / Dec. 2010 26 Standard Speed BinsDDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.DDR3-800 Sp

Rev. 1.6 / Dec. 2010 27 DDR3-1066 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 32.Speed Bin DDR3-1066FUnit NoteCL - nRCD

Rev. 1.6 / Dec. 2010 28 DDR3-1333 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 32.Speed Bin DDR3-1333HUnit NoteCL - nRCD

Rev. 1.6 / Dec. 2010 29 DDR3-1600 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 32.Speed Bin DDR3-1600KUnit NoteCL - nRCD

Rev. 1.6 / Dec. 2010 3 DescriptionThe H5TQ2G83BFR and H5TQ2G63BFR are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Syn-chronous DRAM, ideally

Rev. 1.6 / Dec. 2010 30 DDR3-1866 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 32.Speed Bin DDR3-1866MUnit NoteCL - nRCD

Rev. 1.6 / Dec. 2010 31 DDR3-2133 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 32.Speed Bin DDR3-2133NUnit NoteCL - nRCD

Rev. 1.6 / Dec. 2010 32 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result

Rev. 1.6 / Dec. 2010 33 Package DimensionsPackage Dimension(x8): 82Ball Fine Pitch Ball Grid Array OutlineA1 CORNERINDEX AREA(2.775)(2.350)9.400 0.100

Rev. 1.6 / Dec. 2010 34 Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array OutlineA1 CORNERINDEX AREA(3.250)(2.250)9.000 0.10013.000 0.1000.3

Rev. 1.6 / Dec. 2010 4 ORDERING INFORMATION* xx means Speed Bin GradeOPERATING FREQUENCY* xx means Speed Bin GradePart No. Configuration Power Consump

Rev. 1.6 / Dec. 2010 5 Package Ballout/Mechanical Dimensionx8 Package Ball out (Top view): 82ball FBGA Package1 2 3 4 5 6 7 8 9 10 11A NC VSS VDD NC N

Rev. 1.6 / Dec. 2010 6 x16 Package Ball out (Top view): 96ball FBGA Package1 2 3 4 5 6 7 8 9A VDDQ DQU5 DQU7 DQU4 VDDQ VSS AB VSSQ VDD VSS DQSU DQU6 V

Rev. 1.6 / Dec. 2010 7 Pin Functional DescriptionSymbol Type FunctionCK, CK InputClock: CK and CK are differential clock inputs. All address and contr

Rev. 1.6 / Dec. 2010 8 RESETInputActive Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH

Rev. 1.6 / Dec. 2010 9 ROW AND COLUMN ADDRESS TABLE2GbNote1: Page size is the number of bytes of data delivered from the array to the internal sense a